RVX Tutorial: File I/O

Kyuseung Han
ETRI, Daejeon, South Korea

v2025-10-23 or later

Overview

This tutorial explains how to use file I/O in the RVX SoCs.

Prerequisite

Tutorials with Examples
SW - Standard Library Porting
An RTL simulator with mixed-language support
An FPGA board connected to your computer - Manual

Things to Know

Any part starting with # should be replaced or modified according to your environment.
On Linux, use the bash shell for command-line operations.
On Windows, use the Windows Power Shell for command-line operations.

Location of an Example Platform

#(cloned directory)/rvx_platform_example/test_fileio
This directory will hereafter be referred to as #(example dir).

Converting Input Files to Headers

cmd) cd #(example dir)
cmd) make syn
cmd) ./util/fakefile
cmd) make all

Running an RTL Simulation of a Simple Application

cmd) cd #(example dir)
cmd) make sim_rtl
cmd) cd sim_rtl
cmd) make test_fileio_sim
inst) Check the generated files in ./dump

Generating an FPGA Bitstream

cmd) cd #(example dir)
cmd) make arty-100t // or the FPGA board you have
cmd) cd imp_arty-100t_XXXX // referred to as #(fpga dir)
cmd) make imp

Programming and Validating the FPGA Bitstream

inst) Connect the FPGA board to your computer.
cmd) cd #(fpga dir)
cmd) make program
cmd) make printf
cmd) make hello.all

Running the Example Application

cmd) cd #(fpga dir)
cmd) make test_fileio.all

Retrieving Output Files to a PC

cmd) cd #(fpga dir)
cmd) make dump
inst) Check the generated files in #(fpga dir)/dump

Working with CSV files

Try running the ‘test_matrix_file’ application on both RTL simulation and FPGA prototype.

Applying This to Other Applications

Refer to the ‘File I/O Porting’ section in the manual below:
SW - Standard Library Porting.
Make sure to uncomment ‘USE_FAKEFILE=true’ in #(app dir)/rvx_each.mh.