Overview

• This manual explains how to add or modify clock signals.

Prerequisite

• Tutorials with Examples

Things to Know

• Any part starting with # should be replaced or modified according to your environment.

• On Linux, use the bash shell for command-line operations.

• On Windows, use the Windows Power Shell for command-line operations.

Location of an Example Platform

• #(cloned directory)/rvx_platform_example/test_clock

• This directory will hereafter be referred to as #(example dir).

Defining Clock Signals

• Define the clock signals in your #(platform xml).

• An example is provided in #(example dir)/test_clock.xml.

• You can define new clock signals,

• Or, you can modify the operating frequency of predefined ones.

• Note that defining a clock signal does not guarantee its hardware implementation (PLL).

Implementing PLL in Chip Fabrication

• Due to the different operating speeds of the IPs, multiple clock signals are required inside the SoC.

• To address this, a single clock source (e.g., a crystal oscillator) is typically received from outside the chip, and multiple clock signals are generated through a PLL IP.

• The PLL IP is an analog circuit that cannot be provided in RTL form. It must be designed according to the target fabrication process and is usually available for purchase.

Implementing PLL in RTL Simulation

No action is required for users.
For reference,

• The RVX tool automatically generates a virtual PLL IP for RTL simulation.

• This process occurs when make sim_rtl is executed in #(platform dir).

• The generated file will be located in #(platform dir)/sim_rtl/src.

Implementing PLL in FPGA Prototyping

Automatic Process

No action is required for users for most cases.
For reference,

• The RVX tool automatically generates a TCL script for creating a Vivado PLL IP (.xci) and a module declaration (.v).

• This process occurs when make #(fpga name) is executed in #(platform dir)

  • The generated directory is referred to as #(fpga dir).

• The generated files will be located in #(fpga dir)/xci and #(fpga dir)/src.

Manual Process

The automatic process can sometimes fail because the Vivado PLL IP cannot generate every possible combination of clock signals.
In such cases, you need to check the synthesis failure log for the .xci file and make the necessary corrections.
Depending on the situation, you may also need to modify the clock definition itself.

Predefined Clock Signals

All clocks have a default frequency of 50 MHz unless otherwise assigned.

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